1. Field of the Invention
The present invention relates generally to input circuits for logic circuits having nodes and an operating method therefor, and more particularly, to a circuit receiving an external signal for outputting true and complement signals, suitable for use as a buffer circuit such as an address buffer circuit and a data buffer circuit and as a sense amplifier, in a memory device such as a dynamic RAM (Random Access Memory) and an operating method therefor.
2. Description of the Background Art
FIG. 15 is a schematic block diagram showing a structure of a conventional dynamic RAM. In the dynamic RAM 100 shown in FIG. 15, a clock generator 1 generates various clock signals upon receipt of a row address strobe signal (referred to as RAS signal hereinafter), a column address strobe signal (referred to as CAS signal hereinafter) and a write enable signal (referred to as WE signal hereinafter), to apply the same to a column address buffer 2, a row address buffer 3, a data-in buffer 4 and a data-out buffer 5. On the other hand, externally applied address inputs A.sub.0, A.sub.1, . . . A.sub.n for accessing a memory cell array 6 are applied to the column address buffer 2 and the row address buffer 3. More specifically, row address signals A.sub.0, A.sub.1, . . . A.sub.n are accepted in the row address buffer 3 in response to the fall of the RAS signal and then, column address signals A.sub.0, A.sub.1, . . . A.sub.n are accepted in the column address buffer 2 in response to the fall of the CAS signal. A word line (not shown) is then selected to be activated in a row decoder 7 in response to the row address signals held in the row address buffer 3. Thereafter, for example, in a reading operation, signals stored in memory cells connected to the activated word line are respectively read out to bit lines (not shown). The signals read out are amplified by a (sense amplifier and I/O control circuit) 8 and then, selected by a column decoder 9 in response to the column address signals held in the column address buffer 2, to be applied to the data-out buffer 5. The signals held in the data-out buffer 5 are outputted in response to the clock signals from the clock generator 1.
On the other hand, in a writing operation, an input data signal is written in the memory cell array 6 from the data-in buffer 4 through the I/O control circuit 8.
FIG. 16 is a circuit diagram showing an example of a conventional buffer circuit used as an address buffer circuit in a memory device such as the dynamic RAM shown in FIG. 15 and a static RAM, which is disclosed in, for example, Japanese Patent Publication No. 59-23133.
Description is now made of a structure of a buffer circuit shown in FIG. 16. Transistors used in the buffer circuit shown in FIG. 16 are all n channel MOS transistors. In FIG. 16, transistors Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4 constitute a flip-flop circuit. The transistors Q.sub.1 and Q.sub.2 functioning as load transistors of this flip-flop circuit have their gates receiving a clock .phi..sub.2 from a clock source (not shown). In addition, input nodes N1 and N2 of the flip-flop circuit are connected to each other by a transistor Q.sub.5 having its gate receiving a clock .phi..sub.1 from a clock source (not shown), address signals A and A being extracted from the input nodes. This flip-flop circuit is driven by a transistor Q.sub.6 having its gate receiving a clock .phi..sub.1 from a clock source (not shown). On the other hand, the above described load transistors Q.sub.1 and Q.sub.2 are connected to a power-supply potential Vcc. Transistors Q.sub.7 and Q.sub.9 are connected in series between the node N1 and a ground potential. Transistors Q.sub.8 and Q.sub.10 are connected in series between the node N2 and the ground potential. The transistors Q.sub.7 and Q.sub.8 have their gates receiving the above described clock .phi..sub.1, the transistor Q.sub.9 has its gate receiving an external address signal Ai, and the transistor Q.sub.10 has its gate connected to the node N1.
FIG. 17 is a timing chart for explaining an operation of the buffer circuit shown in FIG. 16. Referring now to FIG. 17, description is made of an operation of the conventional buffer circuit shown in FIG. 16.
First, before the time t.sub.0, the clock .phi..sub.1 is at the "L" level and the clocks .phi..sub.1 and .phi..sub.2 are at the "H" level, so that the nodes N1 and N2 are precharged at the "H" level. The transistor Q.sub.5 equalizes potentials of the nodes N1 and N2.
Then, at the time t.sub.0, when the clock .phi..sub.1 becomes the "H" level and the clock .phi..sub.1 becomes the "L" level, the transistors Q.sub.5 is turned off so that equalizing of the potentials of the nodes N1 and N2 is stopped. At the same time, the transistors Q.sub.6, Q.sub.7 and Q.sub.8 are turned on, so that a potential corresponding to the external address signal Ai applied to the gate of the transistor Q.sub.9 is transmitted to the flip-flop circuit.
For example, if the external address signal Ai is at the "H" level, electric charges at the node N1 are discharged to the ground potential through the transistors Q.sub.7 and Q.sub.9, so that the node N1 becomes the "L" level, whereby the transistor Q.sub.10 is turned off. As a result, charges at the node N2 are not discharged, so that the node N2 remains at the "H" level. Thus, the transistor Q.sub.4 having its gate receiving the "L" level potential at the node N1 is turned off, and the transistor Q.sub.3 having its gate receiving the "H" level potential at the node N2 is turned on. As a result, the address output signal A extracted from the node N2 becomes the "H" level, while the address output signal A extracted from the node N1 becomes the "L" level.
On the other hand, if the external address signal Ai is at the "L" level, electric charges at the node N1 are not discharged, so that the node N1 remains at the "H" level. Thus, the transistor Q.sub.10 having its gate receiving the "H" level potential at the node N1 is turned on. As a result, charges at the node N2 are discharged, so that the node N2 becomes the "L" level. Thus, the transistor Q.sub.4 having its gate receiving the "H" level potential at the node N1 is turned on, and the transistor Q.sub.3 having its gate receiving the "L" level potential at the node N2 is turned off. As a result, the address output signal A extracted from the node N2 becomes the "L" level, while the address output signal A extracted from the node N1 becomes the "H" level.
Meanwhile, the level of the clock .phi..sub.2 is slightly increased by an amount corresponding to a threshold value V.sub.TH of an n channel MOS transistor after the time t.sub.0 as shown in FIG. 17 in order to increase potentials at the nodes N1 and N2 to the potential Vcc quickly, by means of a well known bootstrapped signal generating circuit.
However, in the conventional buffer circuit shown in FIG. 16, a signal applied to the gates of the transistors Q.sub.7 and Q.sub.8 for switching and a signal applied to the transistor Q.sub.6 for driving a flip-flop circuit are the same clock .phi..sub.1. Thus, at the time t.sub.0, when the clock .phi..sub.1 becomes the "H" level, the transistors Q.sub.6, Q.sub.7 and Q.sub.8 are simultaneously turned on. At this time, the transistors Q.sub.1 and Q.sub.2 are not turned off. Consequently, if the external address signal Ai is at the "H" level, electric charges of the node N1 are discharged through the transistors Q.sub.7 and Q.sub.9 while being charged from the power-supply potential Vcc through the transistor Q.sub.1. As a result, discharging of the node N1 is delayed, and transient current unavoidably flows through the transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 and Q.sub.6 from the power-supply potential Vcc to the ground potential, whereby power consumption in the buffer circuit is increased. Such undesirable transient current is referred to as penetrating current hereinafter. In addition, if discharging of the node N1 is delayed, the operating speed of the buffer circuit is reduced.
FIG. 18 is a circuit diagram showing another example of the conventional buffer circuit, which is disclosed in, for example, the U.S. Pat. No. 4,561,702. In addition, FIG. 19 is a block diagram showing a source of various clock signals used in the buffer circuit shown in FIG. 18, and FIG. 20 is a circuit diagram showing a source of a reference potential used in the buffer circuit shown in FIG. 18.
In FIG. 18, p channel transistors Q.sub.11 and Q.sub.12 and n channel transistors Q.sub.13 and Q.sub.14 constitute a CMOS flip-flop circuit. This flip-flop circuit is reset by n channel transistors Q.sub.15 and Q.sub.16 having their gates receiving a clock .phi..sub.3. The clock .phi..sub.3 is obtained by delayinq a RAS signal by a delay circuit 10, as shown in FIG. 19.
Additionally, this flip-flop circuit is connected to a power-supply potential Vcc through p channel transistors Q.sub.17 and Q.sub.18 having their gates receiving a clock .phi..sub.4 and a p channel transistor Q.sub.19 having its gate receiving the clock .phi..sub.3. The clock .phi..sub.4 is obtained by delaying the RAS signal by a delay circuit 11, as shown in FIG. 19.
On the other hand, an external address signal Ai is applied to a gate of a p channel transistor Q.sub.20 through an n channel transistor Q.sub.22 having its gate receiving the clock .phi..sub.3, and a reference potential Vref is applied to a gate of a p channel transistor Q.sub.21 through an n channel transistor Q.sub.23 having its gate receiving the clock .phi..sub.3. A source of this reference potential Vref comprises a resistor having a high resistance value and three stages of PN diodes connected in series between the power-supply potential Vcc and a ground potential, as shown in FIG. 20, which supplies a reference potential Vref (approximately 1.6 V) which is approximately constant irrespective of fluctuations of the power-supply potential Vcc.
A node N3 is connected to gates of a p channel transistor Q.sub.24 and an n channel transistor Q.sub.25 connected in series between the power-supply potential Vcc and the ground potential, an address output signal A being extracted from a node of the transistors Q.sub.24 and Q.sub.25. In addition, a node N4 is connected to gates of a p channel transistor Q.sub.26 and an n channel transistor Q.sub.27 connected in series between the power-supply potential Vcc and the ground potential, an address output signal A being extracted from a node of the transistors Q.sub.26 and Q.sub.27.
FIG. 21 is a timing chart for explaining an operation of the buffer circuit shown in FIG. 18. Referring now to FIG. 21, description is made of an operation of the conventional buffer circuit shown in FIG. 18.
First, before the time t.sub.1, the clock .phi..sub.3 is at the "H" level, so that the transistors Q.sub.22 and Q.sub.23 are on. Thus, the external address signal Ai is applied to the gate of the transist Q.sub.20, and the reference potential Vref is applied to the gate of the transistor Q.sub.21.
If the external address signal Ai is at a higher potential than the reference potential Vref, conductivity (current/voltage), i.e., conductance gm of the transistor Q.sub.21 is larger than that of the transist Q.sub.20. On the other hand, if the external address signal Ai is at a lower potential than the reference potential Vref, conductance gm of the transistor Q.sub.21 is smaller than that of the transist Q.sub.20. At this time, the transistors Q.sub.15 and Q.sub.16 are on, so that charges of the nodes N3 and N4 are both discharged to ground. Thus, the n channel transistor Q.sub.14 receiving a potential of the node N3 and the n channel transistor Q.sub.13 receiving a potential of the node N4 are both off.
Then, when the clock .phi..sub.3 becomes the "L" level at the time t.sub.1, the transistors Q.sub.22 and Q.sub.23 are turned off, so that a potential of the external address signal Ai on this occasion is confined in the node N5 and the reference potential Vref is confined in the node N6. At the same time, the transistors Q.sub.15 and Q.sub.16 are turned off, so that resetting of the nodes N3 and N4 is stopped In addition, the transistor Q.sub.19 is turned on, so that the power-supply potential Vcc for driving the flip-flop circuit is supplied to a node N7.
For example, if the potential of the external address signal Ai is higher than the reference potential Vref, the conductance gm of the transistor Q.sub.21 is larger than that of the transistor Q.sub.20. Thus, more current flows through the transistor Q.sub.21, so that the potential of the node N4 is slightly higher than that of the node N3. A potential difference between the nodes N4 and N3 is amplified by the flip-flop circuit, so that the potential of the node N4 completely becomes the "H" level and the potential of the node N3 completely becomes the "L" level. As a result, the address output signal A extracted from the node N4 through an inverter becomes the "L" level, and the address output signal A extracted from the node N3 through an inverter becomes the "H" level. Meanwhile, the clock .phi..sub.4 applied to the gates of the transistors Q.sub.17 and Q.sub.18 becomes the "L" level after a lapse of a constant time period from the time t.sub.1 in order to hold a potential of the flip-flop circuit.
However, in the conventional buffer circuit shown in FIG. 18, a common clock .phi..sub.3 is applied to the gates of the transistors Q.sub.15 and Q.sub.16 for resetting the nodes N3 and N4 which are output nodes of the flip-flop circuit to the ground potential and the gate of the transistor Q.sub.19 for driving the flip-flop circuit. Consequently, when the clock .phi..sub.3 becomes the "L" level at the time t.sub.1, the flip-flop circuit is driven by the power supply potential Vcc through the transistor Q.sub.19 irrespective of the fact that both the nodes N3 and N4 are at the ground potential and there is no potential difference between the nodes N3 and N4.
In general, since the external address signal Ai is supplied at a TTL level, a potential of 0.8 V or less and a potential of 2.4 V or more must be respectively distinguished as the "L" and "H" levels in the buffer circuit. The reference potential Vref is generally set to approximately 1.6 V which is intermediate between the potentials. For example, if the external address signal Ai is 2.4 V, the transistors Q.sub.20 and Q.sub.21 are not respectively turned off and on but they are both turned on, so that the conductance gm of the transistor Q.sub.21 is slightly larger than that of the transistor Q.sub.20. Thus, when the transistor Q.sub.19 is turned on at the time t.sub.1, a potential difference is small which is transmitted to the input nodes N3 and N4 of the flip-flop circuit from the power-supply potential Vcc through the transistors Q.sub.20 and Q.sub.21. Consequently, much time is required until the potential difference between the nodes N3 and N4 is amplified by the flip-flop circuit so that the transistors Q.sub.11 and Q.sub.14 are turned off and the transistors Q.sub.12 and Q.sub.13 are turned on whereby the nodes N3 and N4 respectively become the "L" and "H" levels after resetting of the flip-flop circuit is stopped at the time t.sub.1. Thus, since penetrating current flows from the power-supply potential to the ground potential from the time t.sub.1 to the time when the transistors Q.sub.11 and Q.sub.14 are turned off, power consumption in the buffer circuit is increased. In addition, since much time is required until the address output signals A and A are outputted, the operating speed of the buffer circuit is reduced.
FIG. 22 is a circuit diagram showing one example of a conventional buffer circuit proposed to solve such problems. In addition, FIG. 23 is a block diagram showing a source of various clock signals used in the buffer circuit shown in FIG. 22.
In FIG. 22, transistors used in this buffer circuit are all n channel MOS transistors. Depletion type transistors Q.sub.28 and Q.sub.29 and enhancement type transistors Q.sub.30 and Q.sub.31 constitute a first flip-flop circuit. This first flip-flop circuit is driven by a transistor Q.sub.32 having its gate receiving a clock .phi..sub.6. The clock .phi..sub.6 is obtained by delaying a RAS signal by a delay circuit 13 and inverting the same by an inverter 16, as shown in FIG. 23.
On the other hand, transistors Q.sub.33 and Q.sub.35 are connected in series between a node N8 and a ground potential, and transistors Q.sub.34 and Q.sub.36 are connected in series between a node N9 and the ground potential. An external address signal Ai is applied to a gate of the transistor Q.sub.33, and a reference potential Vref generated in the circuit shown in FIG. 20 is connected to a gate of the transistor Q.sub.34. In addition, the transistors Q.sub.35 and Q.sub.36 have their gates receiving a common clock .phi..sub.5. This clock .phi..sub.5 is obtained by delaying a RAS signal by a delay circuit 12 and inverting the same by an inverter 15, as shown in FIG. 23.
Additionally, transistors Q.sub.39, Q.sub.40, Q.sub.41 and Q.sub.42 constitute a second flip-flop circuit. The nodes N8 and N9 are respectively connected to gates of the transistors Q.sub.39 and Q.sub.40 through the transistors Q.sub.37 and Q.sub.38. This second flip-flop circuit is driven by a clock .phi..sub.7. The clock .phi..sub.7 is obtained by delaying the RAS signal by a delay circuit 14 and inverting the same by an inverter 17, as shown in FIG. 23. Address output signals A and A are respectively extracted from nodes N10 and N11 of this second flip-flop circuit.
FIG. 24 is a timing chart for explaining an operation of the buffer circuit shown in FIG. 22. Referring now to FIG. 24, description is made of the conventional buffer circuit shown in FIG. 22.
First, before the time t.sub.2, both the clocks .phi..sub.5 and .phi..sub.6 are at the "L" level, and the nodes N8 and N9 are respectively precharged at a power-supply potential Vcc through depletion type transistors Q.sub.28 and Q.sub.29. Then, when the clock .phi..sub.5 becomes the "H" level at the time t.sub.2, the level of the external address signal Ai is transmitted to the first flip-flop circuit.
More specifically, when the external address signal Ai is at the "H" level, charges at the node N8 are discharged through the transistors Q.sub.33 and Q.sub.35, and charges at the node N9 are discharged through the transistors Q.sub.34 and Q.sub.36. On this occasion, since conductance gm of the n channel transistor Q.sub.33 is larger than that of the n channel transistor Q.sub.34, more current flows through the transistor Q.sub.33, so that a potential of the node N8 is lower than that of the node N9. By the above described operation, a potential difference is produced between the input nodes N8 and N9 of the first flip-flop circuit. Thereafter, at the time t.sub.3, the clock .phi..sub.6 becomes the "H" level so that the transistor Q.sub.32 is turned on, whereby the potential difference between the nodes N8 and N9 is amplified by the first flip-flop circuit.
Additionally, the potentials of the nodes N8 and N9 are respectively transmitted to the gates of the transistors Q.sub.39 and Q.sub.40 of the second flip-flop circuit through the transistors Q.sub.37 and Q.sub.38. Then, at the time t.sub.4, the clock .phi..sub.7 becomes the "H" level, whereby the "L" level address output signal A and the "H" level address output signal A are respectively extracted from the nodes N10 and N11.
In this buffer circuit shown in FIG. 22, which is different from the above described buffer circuits shown in FIGS. 16 and 18, the potential difference has been already produced between the input nodes N8 and N9 of the first flip-flop circuit at the time point when the clock .phi..sub.6 becomes the "H" level at the time t.sub.3 so that the first flip-flop circuit is driven. Thus, penetrating current through the flip-flop circuit is decreased and time required until the address output signals are outputted is shortened. Such an address buffer circuit using different clocks as a driving signal for a flip-flop and an address control signal is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 147193/1982.
However, the buffer circuit shown in FIG. 22 has the following problems. FIG. 25 is a diagram showing specifically a part of the timing chart of FIG. 24. Description is now made of a case in which the buffer circuit shown in FIG. 22 is used as a row address buffer of the dynamic RAM.
As shown in FIG. 25, two constraints, i.e., row address set up time (referred to as t.sub.ASR hereinafter) and row address hold time (referred to as t.sub.RAH hereinafter) are established between the RAS signal and the external address signal Ai. More specifically, the effective external address signal Ai must be set before the time point of the fall of the RAS signal by t.sub.ASR and must not be reset until after the time point of the fall of RAS signal by t.sub.RAH. For example, it is provided that t.sub.ASR is 0ns and t.sub.RAH is approximately 10 to 15 ns. On the other hand, in the buffer circuit shown in FIG. 22, the external address signal Ai starts to be transmitted to the buffer circuit in response to the clock .phi..sub.5 which becomes the "H" level by sensing that the RAS signal becomes the "L" level. Thus, if time ta from the time when the RAS signal becomes the "L" level to the time when the clock .phi..sub.5 becomes the "H" level is long, t.sub.ASR may be short, i.e., take a negative value, so that a margin relative to the constraint of t.sub.ASR (for example, 0ns) becomes large. In other words, since the external address signal Ai is loaded into the buffer circuit only after the signal .phi..sub.5 becomes the "H" level, the rise of the signal Ai to the "H" level is permitted to be delayed if the time ta is long. As a result, the time period required for the signal Ai to be set before the fall of the RAS signal, that is, t.sub.ASR is permitted to be negative value. On the other hand, the clock .phi..sub.5 becomes the "L" level again after a lapse of the time tc since it became the "H" level for the purpose of preventing the current from flowing through the transistors Q.sub.35 and Q.sub.33 from the node N8 and preventing effect exerted by the change in the external address signal from being transmitted to the flip-flop circuit. Thus, the shorter time tb from the time when the RAS signal becomes the "L" level to the time when the clock .phi..sub.5 becomes the "L" level again, the shorter t.sub.RAH may be, so that a margin relative to the regulation of t.sub.RAH becomes large. More specifically, the shorter time tc when the clock .phi..sub.5 is at the "H" level, the larger the margins with respect to the constraints of t.sub.ASR and t.sub.RAH become. In order to ensure such satisfactory margins, the pulse duration of the "H" level clock .phi..sub.5 must be short, i.e., 10 ns or less.
However, in an LSI (large-scale integrated circuit) such as a dynamic RAM, a signal having a single and short pulse duration has a dull waveform as represented by a broken line in the clock .phi..sub.5 shown in FIG. 25 due to internal resistance of a signal driving circuit and resistance and stray capacitance of a signal interconnection, so that a potential of an "H" level portion is not substantially increased. Consequently, the conductance gm of the transistors Q.sub.33 and Q.sub.34 are not substantially increased, so that much time is required to discharge charges of the nodes N8 or N9. Thus, an operation of the flip-flop circuit is eventually delayed so that output of the address output signals is delayed.
Conversely, if the pulse duration of the clock .phi..sub.5 is long so that the potential of the "H" level portion is sufficiently increased, the operation of the buffer circuit is delayed.
As described in the foregoing, in the conventional buffer circuit shown in FIGS. 16 and 18, a signal for transmitting an external address signal to a flip-flop circuit and a signal for driving the flip-flop circuit are the same, so that little potential difference is produced at input nodes of the flip-flop circuit at the time of driving the flip-flop circuit. As a result, an operation of the flip-flop circuit is delayed so that penetrating current flows therethrough, and much time is required to output address output signals.
Additionally, in the buffer circuit shown FIG. 22, a signal for transmitting an external address signal to a flip-flop circuit and a signal for driving the flip-flop circuit are different from each other. Even in such a case, if there is only a single switching transistor for controlling transmission of the external address signal to the flip-flop circuit, an independent clock having a short pulse duration is required to control this transistor. However, a potential corresponding to the external address signal is not considerably transmitted due to dullness of the waveform. As a result, an operation of the flip-flop circuit is delayed and much time is required until address output signals are outputted.